U.S. Pat. No. 4,441,198 issued Apr. 3, 1984 to Shibata et al. entitled SHIFT REGISTER CIRCUIT discloses a shift circuit wherein a series of latches provide a sequence of different pulses. More particularly, a first logic circuit comprises coupling gate circuits driven by clock pulses of different phases, flip-flop circuits cascade-connected via the coupling gate circuits and feedback circuits for feeding back the outputs of the flip-flop circuits to the preceding stage flip-flop circuits, and generates pulse sequences of different phases. A second logic circuit further comprises latch circuits one for each of the flip-flop circuits, driven by the pulse sequences generated by the first logic circuit. Those logic circuits are useful to a successive approximation register of a successive approximation A/D converter.
U.S. Pat. No. 4,741,003 issued Apr. 26, 1988 to Katanosaka entitled SHIFT REGISTER CIRCUIT discloses a technique for power reduction including a shift register circuit, having a plurality of stages capable of preserving data bits entered from an external source and shifting the data bits from stage to stage, each of the stages being driven by phase one, phase two and phase three clock signals, each signal alternating between a first and a second logic level. The shift register circuit comprises a first transistor responsive to the phase one clock signal for transferring a new data bit of either first or second logic level, a series combination of second, third, fourth and fifth transistors, and an output node provided between the third and fourth transistors. The second and third transistors are responsive to the new data bit transferred through the first transistor and the phase two clock signal, respectively, to place the phase three clock signal with the logic level corresponding to that of the new data bit at the output node. The fourth and fifth transistors are responsive to a previous data bit transferred to the subsequent stage and the phase three clock signal, respectively, for canceling the logic level of the previous data bit at the output node. This circuit structure results in a reduction in power dissipation.
References teaching a shift register with multi-phases include U.S. Pat. No. 5,260,608 issued Nov. 9, 1993 to Marbot entitled PHASE-LOCKED LOOP AND RESULTING FREQUENCY MULTIPLIER that discloses a circuit wherein a frequency multiplier is embodied by a phase-locked loop including a phase comparator for commanding a plurality of delay elements that furnish successive phase-shift signals to a logical adder made up of EXCLUSIVE OR gates, and U.S. Pat. No. 3,619,642 issued Nov. 9, 1971 to Dunn entitled MULTIPHASE BINARY SHIFT REGISTER that discloses high stability, binary data, multiphase shift register of at least three phases, stores and shifts "N" bits of binary information in binary switches, where N is the maximum number of bits capable of being stored in the shift register at all times during its operation. The binary switches are connected in series and each is then selectively connected to one of the n phases. References that disclose delay lines include U.S. Pat. No. 4,825,109 issued Apr. 25, 1989 to Reynolds entitled DIGITAL DELAY CIRCUIT that discloses a programmable digital delay circuit for controlling the firing of an electroacoustic transducer used in providing an ultrasound image of a fetus under examination, including a clock generator whose output is supplied to a delay line so as to provide a plurality of waveforms shifted in time from one another and from the wave-form generated by the clock generator. Depending on the delay desired prior to firing the transducer, one of the five waveforms may be not be inverted and thereafter used for triggering a counter whose output switches logic gates for enabling a buffer and pulse shaper to fire the transducer, and U.S. Pat. No. 3,622,809 issued Nov. 23, 1971 is Williams entitled ACTIVE DELAY LINE that discloses an electrical delay line including a series of active stages interconnected so that the leading edge of the pulses being propagated through the active stages connected in cascade controls both the turn-on and turnoff of the delayed output pulses to provide delayed pulses .having constant amplitude and constant width.
U.S. Pat. No. 4,567,386 issued Jan. 28, 1986 to Benschop and entitled INTEGRATED LOGIC CIRCUIT INCORPORATING FAST SAMPLE CONTROL discloses a MOS integrated logic circuit which comprises a plurality of groups of combinatory logic elements. These groups form a cascade in that a data output of a preceding group is directly coupled to a data input of a next group within the cascade. During successive clock pulse phases the groups of combinatory logic elements are sampled in the sequence in which they are arranged in the cascade. Charging means provide the charge to be sampled, either by means of a precharge clock phase, or by virtue of being pull-up means.